1. Field of the Invention
The present invention relates to a semiconductor memory device; for example, a static memory (SRAM) and read only memory (ROM). In particular, the present invention relates to a compensating circuit compensating a leakage current of a bit line.
2. Description of the Related Art
For example, when an N-type ROM circuit reads high data, the bit line potential goes low because of a bit line leakage current. For this reason, there is a problem that a read error occurs. There has been known the following N-type ROM circuit in order to solve the foregoing read operation problem by bit line leakage current. The N-type ROM circuit includes a keeper circuit for holding a bit line potential. The keeper circuit solves the read operation problem by the bit line leakage current using on current flowing through a P-channel insulated gate MOS transistor (PMOSFET). However, it is general that the bit line leakage current increases when the circuit becomes high temperature. But, the foregoing on current of the MOSFET of the keeper circuit decreases when the circuit becomes high temperature. Thus, there is a problem that the keeper circuit effect remarkably changes depending on temperature conditions.
Accordingly, it is desired to provide a semiconductor memory device, which can reduce an influence of a read operation by bit line leakage current, and is stabilized so that the foregoing effect does not remarkably change depending on temperature conditions.
Jpn. Pat. Appln. KOKAI Publication No. 2002-208280 discloses a bit line potential pull-up circuit. The bit line potential pull-up circuit compensates a leakage current generated in a bit line, and thereby, prevents an operation delay when a low-power semiconductor memory element is driven and malfunction of a sense amplifier.